test « data - tabellion - Verification tool for VHDL (or at least the prototype of one).

Mode	Name	Size
d---------	CNE_00100	116	log plain
-rw-r--r--	Makefile	2944	log plain
d---------	combinational_processes	179	log plain
-rwxr-xr-x	oracle_creator.py	523	log plain