1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
|
library IEEE;
use IEEE.std_logic_1164.all;
entity invalid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of invalid is
signal s0, s1, s2, s3 : std_logic;
begin
-- Missing:
-- - s1 in sensitivity list.
process (s0, s3)
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
-- Missing:
-- - s1 in sensitivity list.
-- - s0 in sensitivity list.
process (ip3)
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
end case;
end process;
-- Missing
-- - op1 not defined when (s1 != '0').
process (s0, s1)
begin
op2 <= '0';
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others=>
op0 <= s1;
op2 <= '1';
end case;
end process;
-- Missing
-- - op0 not defined when ((s1 == '0') && (s2 = '0')).
process (s0, s1, s2)
begin
op2 <= '0';
case s1 is
when '0' =>
if (s2 = '0')
then
op0 <= s0;
else
op1 <= s1;
end if;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
end;
|
