tabellion - Verification tool for VHDL (or at least the prototype of one).

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Mode	Name	Size
-rw-r--r--	LICENSE	10766	log plain
-rw-r--r--	Makefile	1530	log plain
-rw-r--r--	README.md	1629	log plain
d---------	ast-to-instr	66	log plain
d---------	data	97	log plain
d---------	instr-to-kodkod	138	log plain
d---------	sol-pretty-printer	66	log plain
d---------	time-domains-calculator	36	log plain