Improves CNE_01400, adds test for CNE_01400.

4 files changed, 38 insertions, 0 deletions

diff --git a/data/test/CNE_01400/CNE_01400.pp b/data/test/CNE_01400/CNE_01400.pp
new file mode 100644
index 0000000..d767de2
--- /dev/null
+++ b/data/test/CNE_01400/CNE_01400.pp
@@ -0,0 +1 @@
+($gc.LINE$)
diff --git a/data/test/CNE_01400/invalid.vhd b/data/test/CNE_01400/invalid.vhd
new file mode 100644
index 0000000..5e66b2e
--- /dev/null
+++ b/data/test/CNE_01400/invalid.vhd
@@ -0,0 +1,18 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+
+entity invalid is
+   generic
+   (
+      g_clock_speed0: std_logic;
+      g_clock_speed1: std_logic := '0';
+      g_clock_speed2: natural;
+      g_clock_speed3: natural := 3;
+      g_g_param : std_logic
+   );
+end;
+
+architecture RTL of invalid is
+begin
+end architecture;
diff --git a/data/test/CNE_01400/valid.vhd b/data/test/CNE_01400/valid.vhd
new file mode 100644
index 0000000..0073213
--- /dev/null
+++ b/data/test/CNE_01400/valid.vhd
@@ -0,0 +1,18 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+
+entity valid is
+   generic
+   (
+      clock_speed0: std_logic; -- $SOL:0:0$
+      clock_speed1: std_logic := '0'; -- $SOL:1:0$
+      clock_g_speed2: natural; -- $SOL:2:0$
+      clock_g_speed3: natural := 3; -- $SOL:3:0$
+      i_g_g_param : std_logic -- $SOL:4:0$
+   );
+end;
+
+architecture RTL of valid is
+begin
+end architecture;
diff --git a/data/test/Makefile b/data/test/Makefile
index 323cfeb..37769db 100644
--- a/data/test/Makefile
+++ b/data/test/Makefile
@@ -3,6 +3,7 @@ AST_CREATOR = ghdl --file-to-xml
 #TEST_DIRS ?= $(addprefix ${CURDIR}/,$(wildcard */))
 TEST_DIRS ?= $(patsubst %/,%,$(wildcard */))
 PROPERTY_DIR ?= ${CURDIR}/../property
+# TODO: Start using those variables...
 SOLUTION_DIR ?= /tmp/tabellion/sol/
 ORACLE_CREATOR_SCRIPT = ${CURDIR}/oracle_creator.py
 ################################################################################