Starting to work on test automation.

6 files changed, 375 insertions, 0 deletions

diff --git a/data/test/Makefile b/data/test/Makefile
new file mode 100644
index 0000000..fe2d1ff
--- /dev/null
+++ b/data/test/Makefile
@@ -0,0 +1,23 @@
+TABELLION_MAIN ?= $(shell pwd)/../../
+AST_CREATOR = ghdl --file-to-xml
+TEST_DIRS ?= $(addprefix $(shell pwd)/,$(wildcard */))
+PROPERTY_DIR ?= $(shell pwd)/../property
+SOLUTION_DIR ?= /tmp/tabellion/sol/
+ORACLE_CREATOR_SCRIPT = $(shell pwd)/oracle_creator.py
+################################################################################
+TEST_FILES = \
+	$(addsuffix /valid,$(TEST_DIRS)) \
+	$(addsuffix /invalid,$(TEST_DIRS))
+
+#VHD_FILES = $(addsuffix .vhd, $(TEST_FILES))
+AST_FILES = $(addsuffix .xml, $(TEST_FILES))
+OCL_FILES = $(addsuffix .ocl, $(TEST_FILES))
+SOL_FILES = $(addsuffix .sol, $(TEST_FILES))
+
+all: $(AST_FILES) $(OCL_FILES)
+
+$(AST_FILES): %.xml : %.vhd
+	$(AST_CREATOR) $< > $@
+
+$(OCL_FILES): %.ocl : %.vhd
+	grep -no "\$$SOL:[0-9]\+:[0-9]\+\\$$" $< | $(ORACLE_CREATOR_SCRIPT) > $@
diff --git a/data/test/combinational_processes/combinational_processes.pp b/data/test/combinational_processes/combinational_processes.pp
new file mode 100644
index 0000000..46d6c1e
--- /dev/null
+++ b/data/test/combinational_processes/combinational_processes.pp
@@ -0,0 +1 @@
+($ps.LINE$)
diff --git a/data/test/combinational_processes/invalid.vhd b/data/test/combinational_processes/invalid.vhd
new file mode 100644
index 0000000..37a6c91
--- /dev/null
+++ b/data/test/combinational_processes/invalid.vhd
@@ -0,0 +1,78 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+
+entity invalid is
+   port
+   (
+      ip0, ip1, ip2, ip3:  in std_logic;
+      op0, op1, op2, op3:  out std_logic
+   );
+end;
+
+architecture RTL of invalid is
+   signal s0, s1, s2, s3 : std_logic;
+begin
+   -- Missing:
+   -- - s1 in sensitivity list.
+   process (s0, s3)
+   begin
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+         when others =>
+            op0 <= s1;
+      end case;
+   end process;
+
+   -- Missing:
+   -- - s1 in sensitivity list.
+   -- - s0 in sensitivity list.
+   process (ip3)
+   begin
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+            op1 <= (s0 or s1);
+         when others =>
+            op1 <= (s1 or '0');
+            op0 <= s1;
+      end case;
+   end process;
+
+   -- Missing
+   -- - op1 not defined when (s1 != '0').
+   process (s0, s1)
+   begin
+      op2 <= '0';
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+            op1 <= (s0 or s1);
+         when others=>
+            op0 <= s1;
+            op2 <= '1';
+      end case;
+   end process;
+
+   -- Missing
+   -- - op0 not defined when ((s1 == '0') && (s2 = '0')).
+   process (s0, s1, s2)
+   begin
+      op2 <= '0';
+      case s1 is
+         when '0' =>
+            if (s2 = '0')
+            then
+               op0 <= s0;
+            else
+               op1 <= s1;
+            end if;
+            op1 <= (s0 or s1);
+         when others =>
+            op1 <= (s1 or '0');
+            op0 <= s1;
+            op2 <= '1';
+      end case;
+   end process;
+end;
diff --git a/data/test/combinational_processes/valid.vhd b/data/test/combinational_processes/valid.vhd
new file mode 100644
index 0000000..1703c6a
--- /dev/null
+++ b/data/test/combinational_processes/valid.vhd
@@ -0,0 +1,173 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+
+entity valid is
+   port
+   (
+      ip0, ip1, ip2, ip3:  in std_logic;
+      op0, op1, op2, op3:  out std_logic
+   );
+end;
+
+architecture RTL of valid is
+   type enum_t is (V0, V1, V2, V3);
+   signal s0, s1, s2, s3: std_logic;
+   signal st0: enum_t;
+   signal n0, n1, n2, n3: natural range 0 to 3;
+begin
+   -- $SOL:0:0$
+   s0 <= s1;
+   -- $SOL:1:0$
+   s0 <= (s1 and s2);
+
+   -- $SOL:2:0$
+   process (s0, s1)
+   begin
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+         when others =>
+            op0 <= s1;
+      end case;
+   end process;
+
+   -- $SOL:3:0$
+   process (s0, s1)
+   begin
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+            op1 <= (s0 or s1);
+         when others =>
+            op1 <= (s1 or '0');
+            op0 <= s1;
+      end case;
+   end process;
+
+   -- $SOL:4:0$
+   process (s0, s1)
+   begin
+      op2 <= '0';
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+            op1 <= (s0 or s1);
+         when others =>
+            op1 <= (s1 or '0');
+            op0 <= s1;
+            op2 <= '1';
+      end case;
+   end process;
+
+   -- $SOL:5:0$
+   process (s0, s1, s2)
+   begin
+      op2 <= '0';
+      case s1 is
+         when '0' =>
+            if (s2 = '0')
+            then
+               op0 <= s0;
+            else
+               op0 <= s1;
+            end if;
+            op1 <= (s0 or s1);
+         when others =>
+            op1 <= (s1 or '0');
+            op0 <= s1;
+            op2 <= '1';
+      end case;
+   end process;
+
+   -- $SOL:6:0$
+   with ip0 select
+      s1 <=
+         ip1 when '0',
+         ip2 when '1',
+         ip3 when others;
+
+   -- $SOL:7:0$
+   with st0 select
+      s2 <=
+         ip1 when V0,
+         ip2 when V1,
+         ip3 when V2,
+         s1 when V3;
+
+   -- $SOL:8:0$
+   with st0 select
+      s2 <=
+         ip1 when V0,
+         ip2 when V1,
+         ip3 when others;
+
+   -- $SOL:9:0$
+   process (s0, s1, s2, s3)
+   begin
+      case st0 is
+         when V3 =>
+            op0 <= s0;
+         when V2 =>
+            op0 <= s1;
+         when V1 =>
+            op0 <= s2;
+         when V0 =>
+            op0 <= s3;
+      end case;
+   end process;
+
+   -- $SOL:10:0$
+   process (s0, s1, s2, s3)
+   begin
+      case st0 is
+         when V3 =>
+            op0 <= s0;
+         when V2 =>
+            op0 <= s1;
+         when others =>
+            op0 <= s2;
+      end case;
+   end process;
+
+   -- $SOL:11:0$
+   process (n0, n2)
+   begin
+      case n0 is
+         when 0 =>
+            n1 <= 0;
+         when 1 to 2 =>
+            n1 <= n2;
+         when 3 =>
+            n1 <= 2;
+      end case;
+   end process;
+
+   -- $SOL:12:0$
+   process (n0, n2)
+   begin
+      case n0 is
+         when 0 =>
+            n1 <= 0;
+         when 1 =>
+            n1 <= n3;
+         when 2 =>
+            n1 <= n2;
+         when 3 =>
+            n1 <= 2;
+      end case;
+   end process;
+
+   -- $SOL:13:0$
+   process (n0, n2)
+   begin
+      case n0 is
+         when 0 =>
+            n1 <= 0;
+         when 1 =>
+            n1 <= n3;
+         when others =>
+            n1 <= n3;
+      end case;
+   end process;
+end;
diff --git a/data/test/combinational_processes/valid_unsupported.vhd b/data/test/combinational_processes/valid_unsupported.vhd
new file mode 100644
index 0000000..f38c06e
--- /dev/null
+++ b/data/test/combinational_processes/valid_unsupported.vhd
@@ -0,0 +1,82 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+
+entity valid is
+   port
+   (
+      ip0, ip1, ip2, ip3:  in std_logic;
+      op0, op1, op2, op3:  out std_logic
+   );
+end;
+
+architecture RTL of valid is
+   signal s0, s1, s2, s3 : std_logic;
+begin
+-- Add some vectors.
+-- Add some enums.
+
+   s0 <= s1;
+   s0 <= (s1 and s2);
+
+   process (s0, s1)
+   begin
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+         when others =>
+            op0 <= s1;
+      end case;
+   end process;
+
+   process (s0, s1)
+   begin
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+            op1 <= (s0 or s1);
+         when others =>
+            op1 <= (s1 or '0');
+            op0 <= s1;
+      end case;
+   end process;
+
+   process (s0, s1)
+   begin
+      op2 <= '0';
+      case s1 is
+         when '0' =>
+            op0 <= s0;
+            op1 <= (s0 or s1);
+         when others =>
+            op1 <= (s1 or '0');
+            op0 <= s1;
+            op2 <= '1';
+      end case;
+   end process;
+
+   process (s0, s1, s2)
+   begin
+      op2 <= '0';
+      case s1 is
+         when '0' =>
+            if (s2 = '0')
+            then
+               op0 <= s0;
+            else
+               op0 <= s1;
+            end if;
+            op1 <= (s0 or s1);
+         when others =>
+            op1 <= (s1 or '0');
+            op0 <= s1;
+            op2 <= '1';
+      end case;
+   end process;
+
+   with ip0 select
+      s1 <=
+         ip1 when '0',
+         ip2 when '1',
+         ip3 when others;
+end;
diff --git a/data/test/oracle_creator.py b/data/test/oracle_creator.py
new file mode 100755
index 0000000..8ef5a14
--- /dev/null
+++ b/data/test/oracle_creator.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+import sys
+
+solutions = list()
+
+for line in sys.stdin.readlines():
+    line_data = line.split(":")
+    line_number = line_data[0]
+    solution_number = int(line_data[2])
+    solution_item_number = line_data[3].replace("$",'')
+
+    if (len(solutions) <= solution_number):
+        solutions.insert(solution_number, list())
+
+    solutions[solution_number].insert(int(solution_item_number), line_number)
+
+for sol in solutions:
+    print("(" + (' '.join(sol)) + ")")