parser « instr-to-kodkod - tabellion - Verification tool for VHDL (or at least the prototype of one).

Mode	Name	Size
-rw-r--r--	Makefile	1532	log plain
-rw-r--r--	PropertyLexer.g4	868	log plain
-rw-r--r--	PropertyParser.g4	31112	log plain