From 72b3069a20b8573ceff73b27936a76213aacc344 Mon Sep 17 00:00:00 2001 From: Nathanael Sensfelder Date: Thu, 20 Jul 2017 17:34:51 +0200 Subject: Adds Simple Signal Assignment Statement Node. --- ast-to-instr/src/VHDLProcess.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ast-to-instr/src/VHDLProcess.java') diff --git a/ast-to-instr/src/VHDLProcess.java b/ast-to-instr/src/VHDLProcess.java index 5d49b40..36634fe 100644 --- a/ast-to-instr/src/VHDLProcess.java +++ b/ast-to-instr/src/VHDLProcess.java @@ -439,7 +439,7 @@ public class VHDLProcess extends ParsableXML "ref" ); - if (!Main.node_is_function_or_literal(ref)) + if (!Main.node_is_function_or_literal(xml_id)) { Predicates.add_entry ( -- cgit v1.2.3-70-g09d2