tabellion - Verification tool for VHDL (or at least the prototype of one).

Age	Commit message (Collapse)	Author
2017-07-21	Adds "port maps" support.	Nathanael Sensfelder

2017-07-21	Working on the components. Found error in scripts.	Nathanael Sensfelder

2017-07-21	Optimization pass.	Nathanael Sensfelder

2017-07-21	Completes When Node parsing.	Nathanael Sensfelder

2017-07-20	Still missing: Components, When Nodes, Outputs.	Nathanael Sensfelder

2017-07-20	Fixes stupid mistakes, adds some nodes.	Nathanael Sensfelder

2017-07-20	Adds Simple Signal Assignment Statement Node.	Nathanael Sensfelder

2017-07-20	Working on the IF nodes + Childrens -> children.	Nathanael Sensfelder

2017-07-20	Working on the "internal_process.py" translation.	Nathanael Sensfelder
	I think I've found some not-too-ugly solution.
2017-07-20	Still working on AST-to-Instr.	Nathanael Sensfelder

2017-07-20	Continuing the implementation of AST-to-Instr.	Nathanael Sensfelder

2017-07-20	Adds more types parsed from XML.	Nathanael Sensfelder

2017-07-19	Starting a Java implementation of ast-to-instr.	Nathanael Sensfelder
	Keeping things clean, this time.