3 files changed, 60 insertions, 0 deletions
diff --git a/data/test/CNE_01100/CNE_01100.pp b/data/test/CNE_01100/CNE_01100.pp
new file mode 100644
index 0000000..33109d4
--- /dev/null
+++ b/data/test/CNE_01100/CNE_01100.pp
@@ -0,0 +1 @@
+($pt.LINE$)
diff --git a/data/test/CNE_01100/invalid.vhd b/data/test/CNE_01100/invalid.vhd
new file mode 100644
index 0000000..3703c47
--- /dev/null
+++ b/data/test/CNE_01100/invalid.vhd
@@ -0,0 +1,31 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+
+entity invalid is
+   port
+   (
+      i_ip0: in std_logic;
+      i_clock: in std_logic;
+      i_o: in std_logic;
+      i_o_reset: in std_logic;
+      i_o_b_reset: in std_logic;
+      i_i_reset: in std_logic;
+      o_ip0: out std_logic;
+      o_clock: out std_logic;
+      o_o: out std_logic;
+      o_i_reset: out std_logic;
+      o_o_reset: out std_logic;
+      o_o_b_reset: out std_logic;
+      b_ip0: inout std_logic;
+      b_clock: inout std_logic;
+      b_o: inout std_logic;
+      b_i_reset: inout std_logic;
+      b_o_reset: inout std_logic;
+      b_b_o_reset: inout std_logic
+   );
+end;
+
+architecture RTL of invalid is
+begin
+end architecture;
diff --git a/data/test/CNE_01100/valid.vhd b/data/test/CNE_01100/valid.vhd
new file mode 100644
index 0000000..41f04e2
--- /dev/null
+++ b/data/test/CNE_01100/valid.vhd
@@ -0,0 +1,28 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+
+entity valid is
+   port
+   (
+      ip0: in std_logic; -- $SOL:0:0$
+      b_i_ip1: in std_logic; -- $SOL:1:0$
+      not_i_ip2: in std_logic; -- $SOL:2:0$
+      o_ip3: in std_logic; -- $SOL:3:0$
+      b_ip4: in std_logic; -- $SOL:4:0$
+      op0: out std_logic; -- $SOL:5:0$
+      b_o_op1: out std_logic; -- $SOL:6:0$
+      not_o_op2: out std_logic; -- $SOL:7:0$
+      i_op3: out std_logic; -- $SOL:8:0$
+      b_op4: out std_logic; -- $SOL:9:0$
+      bp0: inout std_logic; -- $SOL:10:0$
+      o_b_bp1: inout std_logic; -- $SOL:11:0$
+      not_b_bp2: inout std_logic; -- $SOL:12:0$
+      i_bp3: inout std_logic; -- $SOL:13:0$
+      o_bp4: inout std_logic -- $SOL:14:0$
+   );
+end;
+
+architecture RTL of valid is
+begin
+end architecture;